Over the past few years, flat panel displays such as liquid crystal displays and electroluminescent (EL) displays have become the main trends in displays. This type of FPD is constructed by enclosing liquid crystal or EL elements, which are the elements used for display, in a TFT array that arranges a plurality of pixels in a matrix.
FIG. 5 shows a TFT array 10 of a typical liquid crystal display. The TFT array 10 is constructed from a plurality of pixels (i.e., 50) arranged in a matrix, pixel selection lines (i.e., 20, 30) for selecting the display pixels, and pixel selection circuits 11, 12 for controlling the pixel selection lines.
A pixel 50 is constructed from a switching transistor 52 (pixel selection switch) where pixel selection lines 21, 32 are connected to the drain terminal and the gate terminal, respectively, and a capacitor 51 connected to the source terminal of the switching transistor 52. The liquid crystal enclosed in the TFT array 10 is controlled by the voltage of the capacitor 51. In FIG. 1, one terminal of the capacitor 51 is grounded, but is sometimes connected to a specified voltage source installed externally without grounding depending on the usage state of the TFT array.
For a TFT array used in an EL display, the pixel structure shown in FIG. 6 is typical. The difference from pixel 50 in FIG. 5 is a transistor 81 for driving the EL element is connected on the source side of the switching transistor 52. Since the EL element 81 (not enclosed in the TFT array state) is a light-emitting element wherein the emitted light brightness is changed by the drive current, the voltage charged in the capacitor 51 is converted into current by the transistor 81.
The pixel selection lines are constructed from a plurality of gate lines 31, 32, 33 and a plurality of data lines 20, 21, 22. The display pixel at an intersection is selected by selecting the gate line and the data line connected to the display pixel. For example, pixel 50 at an intersection is selected by selecting gate line 32 and data line 21. The gate lines 31, 32, 33 are digital signal lines, and have +5 V applied in the selected state and 0 V applied in the not-selected state. The data lines 20, 21, 22 are analog signal lines, and the voltage charged in the capacitor 51 in the pixel 50 is applied. In other words, the data lines 20, 21, 22 are the pixel selection lines combining both the function of specifying the position of the display pixel and the function of applying the voltage for controlling the liquid crystal for the display pixel.
The pixel selection circuits 11, 12 are constructed from a vertical pixel selection circuit 11 and a horizontal pixel selection circuit 12. The vertical pixel selection circuit 11 inputs an external signal that becomes the liquid crystal control voltage (voltage from voltage source 45 in FIG. 5) to the data lines connected to the display pixels. The horizontal pixel selection circuit 12 applies +5 V to the gate lines connected to the display pixels.
A method for testing the TFT array 10 is a method that charges the capacitor 51 of a pixel and measures the electric charge or the voltage (see Japanese Kokai Unexamined Patent 2003-43,945 and Kokai Unexamined Patent H10[1998]-96,754). This method for testing is described with reference to FIGS. 5 and 7 below. In the test, a voltmeter 42 and a switch 41 are connected at the input of the vertical pixel selection circuit 11, and a voltage source 45 having an output voltage V is connected to the other terminal of the switch 41.
Initially, the switch 41 is set in the “on” state. Gate line 32 of pixel 50, which is the test subject, is selected and a voltage V is applied to the data line 21 by the pixel selection circuits 11, 12. Then the switching transistor 52 of the pixel 50, which is the device under test, enters the “on” state, and the voltage V is charged in the capacitor 51. Next, the switch 41 is set in the “off” state, the voltage application to the data line 21 stops, and the voltage of the data line 21 is measured by the voltmeter 42. If both the switching transistor 52 and the capacitor 51 are operating normally, the data line 21 should maintain the voltage V. Since the measured voltage of data line 21 does not become V when the switching transistor 52 is not operating, and a pixel defect such as poor charging of the capacitor 51 has occurred, the presence or absence of a pixel defect can be determined by measuring the voltage V of data line 21. Finally, the discharge cycle is executed wherein the voltage of the voltage source 45 is set to 0 V, the switch 41 is set in the “on” state, and the capacitor 51 discharges. This procedure tests the quality of all of the pixels and evaluates the quality of the TFT array 10.
A TFT array 80 for an EL display can be tested by a similar procedure because the circuit structure in the stage before the transistor 81 for driving is no different than in pixel 50 for the liquid crystal.
In the test described above, since the cycle of charging, measuring, and discharging of each pixel in the TFT array 10 is repeated, the problem is the long time needed until the measurement of the entire TFT array 10 is completed.